Non-volatile memory devices find widespread application in electronic systems that do not receive continuous power, for example in applications where power is not always available, where power is frequently interrupted, and/or where low-power usage is desired. Example applications include mobile telecommunication systems, memory cards for storing music and/or image data, and system on a chip applications that include a processing unit and a memory unit.
Cell transistors in non-volatile memory devices commonly employ a stacked gate structure that is formed over a channel region of a substrate between source/drain regions. The stacked gate structure includes a sequentially stacked gate insulating layer formed on the channel, floating gate electrode, inter-gate dielectric layer and control gate electrode. The floating gate electrode and the control gate electrode are capacitively coupled to allow for programming of the floating gate during a programming stage of the transistor. At the same time, the floating gate electrode is isolated between the gate insulating layer and the inter-gate dielectric layer to prevent the migration of charge from the floating gate to the substrate or from the floating gate to the control gate during operation of the transistor following the programming stage.
The gate insulating layer is commonly formed of a gate oxide material such as SiO2. The floating gate formed on the gate insulating layer comprises a conductive material such as polysilicon. The inter-gate dielectric layer is formed on the floating gate. A control gate comprising a conductive material such as polysilicon is then formed on the inter-gate dielectric layer. The inter-gate dielectric layer must therefore be sufficiently thin to provide for adequate capacitive coupling between the control gate and the floating gate during the programming stage to allow for charge flow so that charge can be stored in the floating gate. Also, a thin inter-gate dielectric layer results in increased device speed. At the same time, the inter-gate dielectric layer must be sufficiently thick to prevent the migration of charge from the floating gate to the control gate during operation of the transistor following programming.
The stacked gate structure can be reduced schematically to two capacitors in series between a control voltage Vcontrol applied to the control gate and a substrate voltage, for example a ground voltage, applied to the substrate. A first capacitance (C1) is provided between the control gate and the floating gate, and a second capacitance (C2) is provided between the floating gate and the substrate. The resulting voltage of the floating gate is therefore determined according to the relationship has the relationship Vfloating=Vcontrol C1/(C1+C2). During a charging operation, a large positive voltage is applied to the control gate relative to the substrate. Electrons migrate from the substrate and penetrate into the floating gate through the gate insulating layer. The floating gate is thus provided with an initial voltage Vfloating. A large first and second capacitance tends to maintain the initial voltage of the floating gate. Conversely, during a discharge operation, a negative voltage is applied to the control gate, and a positive voltage is applied to the substrate. During a discharge operation, the electrons previously stored in the floating gate are released back into the substrate through the gate insulating layer. The amount of charge in the floating gate changes the threshold voltage of the transistor. In this manner, a charged transistor is interpreted as a first binary value, for example, a “1”, and a discharged transistor is interpreted as second binary value, for example, a “0”, during a read operation of the transistor.
In non-volatile memory devices, the characteristics of the inter-gate dielectric layer used for isolating the floating gate from the control gate are of primary consideration. The inter-gate dielectric layer must be capable of preventing migration of electrical charge from the floating gate to the control gate. For this reason, a thick inter-gate dielectric layer is desired. At the same time, the dielectric layer should be as thin as possible to ensure capacitive coupling between the control gate and floating gate during a programming operation. Floating-gate memory devices commonly require a high programming voltage for carrying out the charge and discharge operations. For example, contemporary flash cells operate in programming mode using an 18 volt potential between the control gate and the substrate. Contemporary electrically erasable programmable read only memory (EEPROM) devices require a 15 volt potential. Specialized pumping circuits are used to generate such a high voltage on the chip, and specialized high-voltage transistors are required for applying the high voltage to the device terminals. Such large-scale components tend to consume valuable chip surface area, and tend to raise the manufacturing costs.
Some have proposed formation of the inter-gate dielectric layer entirely of SiO2, or “oxide”. However, if oxide is used alone as the inter-gate dielectric, it must be formed in a layer of at least 150 Å in thickness for preventing migration of charge from the floating gate to the control gate and to prevent the surface roughness of the underlying polysilicon floating gate from transferring to the floating gate. Such a thick layer requires an excessively high programming voltage to ensure capacitive coupling between the control gate and the floating gate.
Others have proposed an inter-gate dielectric layer formed of silicon nitride SiN3, or “nitride”. A nitride inter-gate dielectric layer provides for enhanced capacitive coupling between the control gate and the floating gate, per unit of thickness, as compared to an oxide inter-gate dielectric layer. However, nitride does not adhere well to the polysilicon material in the control gate and floating gate and therefore is impractical for use alone as an inter-gate dielectric material.
In view of this, others have proposed a layered combination of oxide-nitride-oxide (ONO) layers for forming the inter-gate dielectric layer. In an ONO layer, the beneficial capacitive coupling effects of the nitride layer are realized, while the lower and upper oxide layers provide for a transition, or buffer layer, between the nitride dielectric layer and the polysilicon control gate and floating gate. However, in this configuration, due to the surface roughness of the floating gate which is at least 40 Å in height, the lower oxide layer in contact with the floating gate must be formed to a thickness of at least 60 Å in order to adequately cover the underlying topology. Since the lower oxide layer has conforming characteristics, the topology of the underlying top surface of floating gate is translated to the upper surface of the lower oxide layer This is followed by a nitride layer of 80 Å in thickness. Since the nitride layer also has conforming characteristics, the topology of the underlying top surface of oxide layer is translated to the upper surface of the nitride layer. A second oxide layer of 60 Å in thickness is then deposited on the nitride layer. This layer, referred to as a blocking oxide layer, prevents diffusion of charge between the floating gate and the control gate. The resulting structure is thus 190 Å in thickness, which limits the amount to which the programming voltage of the device can be lowered.